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[July 2002]
Promising Insulator Material May Enable Smaller, Faster Semiconductors
The DigitalDNA Laboratories of Motorola's Semiconductor Products Sector (SPS) - along with Nanjing University and the Institute of Physics of the Chinese Academy of Sciences (CAS) - have characterised the excellent material properties of lanthanum aluminate films. These properties are said to make this material one of the strongest potential candidates for a new gate insulator for smaller, faster CMOS integrated circuits of the future.By pushing out the limits of the semiconductor industry's 'Moore's Law', thereby enabling continued scaling down in chip size, lanthanum aluminate (LAO) and lanthanum aluminium oxynitride (LAON) could replace the silicon dioxide as a gate dielectric in MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices for the 65 nanometer technology node and beyond without requiring extensive modification of the manufacturing equipment or process flow.
The prognosis results from a two-year joint research project focussed on high dielectric constant materials between Motorola and two members of China's top research community. The combination of separate, concurrent research between Motorola and each institution over this period has developed into a strategic research partnership among the three organisations.
Many materials are currently under consideration within the industry as potential replacements for silicon dioxide as the gate dielectric material for 65nm CMOS technology. However, states Motorola, most of these materials, which have a dielectric constant greater than 20, either are not thermodynamically stable in direct contact with silicon or generate diffusion problems, which cause significant degradation of device performance.
LAO and LAON demonstrate the best thermal stability among all known possible high dielectric constant materials and can also be economically integrated into a traditional CMOS process flow.
Traditional device materials reach fundamental physical limits when the scaling continues down to deep submicron levels (below 0.10 micron). As device dimensions continue to scale down, the thickness of the silicon dioxide layer must also decrease to maintain the same capacitance between the gate and channel regions. The 65nm generation requires a thickness of less than 2nm.
ENDS