Processing & Manufacturing Support

Cleanliness Validation

The cleanliness of surfaces at all stages of wafer, device and PCB production is paramount to performance. The tolerable level of cleanliness at each production stage may vary considerably, hence the need for a range of surface sensitive analytical techniques to match requirements. X-ray Photelectron Spectroscopy (XPS) and Time of Flight Secondary Ion Mass Spectrometry (ToFSIMS) have proved an unbeatable combination for elemental, chemical state and molecular information on a wide range of cleanliness issues, from stain residues after wash cycles on silicon wafers to bond pad contamination on PCBs.

A typical cleaning validation project would include the following:

• Chemical characterisation of contaminants
• Effects of each manufacturing process stage on surface condition
• Production of finalised cleaning specification
• Characterisation of reagents to be used
• Assess Cleaning Stages and Final validation
• Continued System Monitoring.

We also provide a cleanliness validation package, Validata, which allows ongoing assessment of cleaning efficacy, even when process steps are modified.

Monitoring Dopant Levels

Dopants are the key elements which are deliberately added to semiconductor materials to provide the required electrical performance characteristics. For example, boron, arsenic and phosphorus in silicon wafers may be present in concentrations from ~1 atomic % to below ppm levels. These dopants are typically placed within a specific depth region of a semiconductor substrate using ion implantation, MBE or MOVPE techniques. Manufacturers therefore need to know the precise dose levels, profile shape and depth characteristics e.g. junction depth of dopants within their materials. Dynamic Secondary Ion Mass Spectrometry is the technique of choice for concentration depth profiling of semiconductor materials. For shallow implants and growth structures Ultra Low Energy SIMS (ULESIMS) is used where the energy of the incident ion beam is reduced to levels typically in the range 500eV to 3keV.

Solving Yield Issues

Solving yield problems can have a major beneficial impact on profitability in the semiconductor industry. Any process deviation, ranging from a change in materials supplier, different cleaning regime or environmental factors can impact on yields. Ceram has well-established protocols for diagnosing the exact source of yield problems whether it is a surface-related issue or buried within the structure of the device. Experience has shown that a systematic series of tests, designed to measure key physical and/or chemical features of the materials, is a far more cost effective route to a final solution than costly trial-and-error repetition.

A typical protocol may include:

• Chemical analysis of batches of input materials, including solvents and other reagents
• Use of witness coupons to monitor changes in environmental conditions or contaminants within the production facility
• Analyse device wafers or PCBs at mid- production points to assess any onset of defects
• Compare retained production samples if available.